1. Field of the Invention
The present invention relates software tools used in computer aided design (CAD) of integrated circuits, and more specifically to a method and apparatus for facilitating validation of entire integrated circuits in parallel with development of blocks in a hierarchical design approach.
2. Related Art
Integrated circuits (ICs) are generally designed in number of design stages using different design tools. Design tools provides various design data in the form of file. For example, a netlist provides the connection details of the integrated circuit, another file provides the description of the layout of gates/components. The design data available from each stage of the design process is provided to various modeling, simulation/test tools to measure performance metrics (or constraints) such as timing, size, etc.
However, with the increasing number of design elements (e.g. multi million gates etc) in an integrated circuit, the performance requirements may increasingly become stringent. Design process may become complex and difficult to manage due to correspondingly increased amount of data generated by design tools supporting such large scale design.
Hierarchical design approaches are often used to address such complex and large integrated circuit designs. In a hierarchical design approach, the design is divided into a number of manageable blocks or sub-chips (connected potentially by corresponding interface/glue logic). Different groups can potentially work on different blocks in parallel. In general, the design (including testing, measurement of various metrics related to constraints) of each block is completed in several stages (“design stages”). Design tools such as “First Encounter” (available from Cadence Design Systems, San Jose, Calif. 95134, 408.943.1234) can be used to divide the total design into the blocks or sub-chips.
According to one known prior hierarchical design approach, the blocks are independently designed, and each block is then verified for constraints such as timing, size, etc. After completion of design of all the blocks, various data (e.g., generated during the block design in the form of files) representing the block size and shape, I/O (input/output), timing, pin locations, and other information required for the top level design process are provided to a top level design process (described below).
In a top level design, the data received from design of all the individual blocks is used to validate/test the entire integrated circuit, along with any contained glue logics. One disadvantage with such an approach is, the increase in design time as the top level design is started only after completion of design of all the blocks.
Hence what is needed is a method and apparatus for facilitating validation of entire integrated circuits in parallel with development of blocks in a hierarchical design approach.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.